Energy Modeling for LLM Inference without Per-Workload Profiling
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Energy Modeling for LLM Inference without Per-Workload Profiling

Abstract

Predicting energy for graphics processing units before a large language model workload is deployed requires both its active duration and the activity generated while it runs. This work develops an interpretable energy model for inference on NVIDIA A100 graphics processing units. It separates static energy, which is proportional to active time, from dynamic energy, whose compute term scales with issued floating-point operations and whose memory terms scale with bytes transferred at shared memory, the level-two cache, and high-bandwidth memory. A memory-level count denotes bytes crossing that level's interface with the level beneath it; loads and stores therefore use the same per-byte coefficient. Published microbenchmarks of graphics processors supply compute, memory, latency, bandwidth, and event-energy parameters, limiting local profiling to idle static power and one fixed timing overhead rather than fitting workload-specific energy curves. For inference distributed across graphics processing units, this work additionally contributes a system-wide network model whose energy scales with collective active time, transmitted bytes, and reduction-memory traffic. The energy equations depend on an execution-aware Roofline analysis that predicts kernel active time and activity counters from thread-block geometry, resource concurrency, full and tail waves, pipeline fill and drain, and explicit memory traffic. RAPID-LLM composes these kernel profiles into large language model inference graphs and tracks the scheduled collective communication activity. On held-out A100 data, the model achieves 11.41\% general matrix multiplication energy mean absolute percentage error. End-to-end single-device energy mean absolute percentage error is 13.5\% for Qwen workloads and 17.3\% for Llama decode; two- and eight-device Qwen 2.5 72B experiments obtain 14--20\% system-energy mean absolute percentage error. Independent counter validation shows close agreement for high-bandwidth-memory and level-two-cache traffic, supporting energy attribution to explicit compute, memory, and static terms.