UCLA

This dissertation consists of two parts. In the first part, a broadband universal receiver is proposed with channel selection and blocker rejection that achieves a low noise figure and high linearity through an innovative use of feedback techniques. It also demonstrates ample harmonic rejection owing to its newly proposed harmonic trap method with no calibration required. Realized in 28-nm CMOS technology, the receiver exhibits a noise figure of 2.1 dB and a third and fifth harmonic rejection of more than 60.8 dB up to 2 GHz while consuming 49 mW.

In the second part, we introduce a a new linear, time-variant model that provides a general framework for understanding and modeling of injection locking in oscillators and frequency dividers. Application of the proposed model to direct injection locked frequency dividers (DILFDs) results in new insights and design optimization criteria which highly improves the divider lock range and power consumption. Two DILFD prototypes have been fabricated: A 1.88-mW single DILFD that operates from 26 GHz to 63 GHz and a 4.76-mW coupled DILFD that operates from 24 GHz to 73 GHz with no need for tuning or adjustments.