UC San Diego

5G wireless technologies have been developed for many years, and is meant to deliver multi-Gbps peak data rates, ultra low latency, and massive data capacity. With the recent advances in communication systems at > 100 GHz, the so-called beyond 5G or 6G have been enabled at the wide sub-THz spectrum, which is unlicensed and and has few interferers due to low radiated power and high space loss factor at this frequency range. This frequency range is now available for promising applicatoins, such as low-range Internet-of-Things (IoT), advanced or virtual reality (AR/VR), immersive tourism, etc.

This dissertation focuses on building high performance and low cost phased-array systems and the related circuits at D-band in an advanced CMOS silicon-on-insulator (SOI) process for short-range and high data rate communications. It presents eight-element receive (RX) and transmit (TX) wafer-scale phased-array systems with on-chip antennas at around 140 GHz. The antenna arrays are fabricated on the quartz wafer and attached to the chip wafer, and electromagnetic (EM) coupled to on-chip antenna feeds. Both arrays are wirebonded on low-cost printed circuit boards (PCB). A high-IF beamforming architecture is introduced at 140 GHz for low single sideband (SSB) noise figure (RX) and high in-band linearity (TX). An IF beamformer (phase and amplitude control) at 10-20 GHz is easier to implement with lower power consumption and RMS errors than an RF beamformer.

This dissertation also presents D-band power amplifiers (PAs) in CMOS SOI as the front-end circuits for transmitters or phased-array transmitters. A multi-way power combining technique is introduced and employed to realize PAs high output power and efficiency.

Record results in system NF and EIRP are demonstrated for RX and TX arrays, together with > 10 Gbps communication links for TX and RX systems and using 64-QAM waveforms. The presented PAs also achieve record saturation power (Psat), output 1-dB compression power (OP1dB) and power added efficiency (PAE), compared to the prior art in CMOS.