A methodology for software-hardware codesign
In this report we present two appraoches for synthesis of real-time systems with a minimal number of application specific integrated circuits (ASICs) while still meeting the required performance constraints. One approach starts with a single process description which can be easily compiled into a software implementation for any standard processor. If this software implementation does not satisfy the required performance, descriptions of the performance-critical parts are extracted out and implemented as ASICs. The other approach starts with a description written as multiple processes communicating through global signals. The description can be naturally mapped to a hardware-only implementation in which each process is implemented as one ASIC. In order to minimize number of ASICs, the processes are merged and split for mapping to a combination of standard processors and ASICs. The step-wise refinement process for both approaches is demonstrated on an example of a real-time system. Issues and tools regarding the automation of the proposed codesign methodology are also discussed.