UC Berkeley

The works investigate reliability and performance enhancement for ultra-scaled advanced CMOS and memory devices through experimental characterization, physical modeling, and device simulation. The study first examines random telegraph noise (RTN) in advanced transistors under cryogenic operation, revealing the strong dependence of carrier trapping dynamics on temperature and bias conditions. A physics-based RTN modeling framework, combined with experimental results, is developed to predict RTN behavior in nanoscale transistors. In addition, the impact of ultra-thin aluminum incorporation within high-k metal gate stacks (HfO₂/TiN) is investigated. Electrical characterization and material analyses reveal that aluminum modifies the effective work function through oxygen scavenging from the TiON layer. The reliability trade-offs associated with Al incorporation in the metal gate are further clarified. Next, to mitigate the side effects of Al-incorporated gates, an oxygen insertion (OI) technology is proposed as an alternative approach for controlling the flat-band voltage. Lastly, a silicon-germanium/silicon (SiGe/Si) heterojunction drain transistor is proposed for 3D NAND flash memory to enhance gate-induced drain leakage (GIDL) and improve erase speed through increased band-to-band tunneling. Simulation results demonstrate significant improvement in erase performance without degrading inhibit-mode operation.