UCLA

The Semiconductor industry is a multi-billion dollar industry and Semiconductor Yield is a fundamental factor driving device cost. Development cost, time-to-market & yield are the most important factors of interest to the industry. Two major components are associated with Semiconductor Yield: 1. Defect Limited Yield 2. Parametric-Shift limited Yield. Parametric Yield is influenced by process variations for a given design and process node.Several models from literature which predict Defect-Limited yield based on primarily two parameters: Defect Density and Area of the Die. A “yield calculator” is developed that incorporates all Defect-limited models and allows the user to compare yield estimates among multiple models, or inversely estimate Defect Density, and calculate model parameters based on Foundry-provided Defect Density values and Wafer Sort (WS) test yield data. The methodology also includes a Bayesian formulation for aggregating yield estimates from various models in the form of an uncertainty distribution. This study also proposes a Process Adjustment Factor (PAF) to the models to better estimate the variation of yield across various process nodes. PAF is estimated using a geometric probability approach using process-based factors such as Metal Pitch, Metal Width etc. PAF is used to adjust yield, and the results are compared with 4 different Application Specific Integrated Circuits (ASICs) at the 40nm and 65nm process nodes.Many factors influence Parametric-Shift, with the most influential being process variations for a given process technology. Parametric shift is often estimated by circuit simulations which is both time consuming and costly. A simpler method is proposed which uses a machine learning + copula approach to model the complex relations contributing to parametric shift using Wafer Acceptance Test (WAT) data and WS Data (screened for yield loss due to parametric shift failures only). While Foundries do not share process-related data, they provide WAT data which are obtained from test coupons placed at specific locations on the wafer. WAT data records fundamental electrical parameters such as Oxide Thickness, Threshold Voltage, Saturation Current etc. and these recordings provide a window for observing process fluctuations. Trained Gaussian Copulas are used to generate Synthetic data for WAT parameters of a device and use trained machine learning Models (LGBM and XGBoost) to estimate yield with training accuracies of up to 94%.Process node data is used in conjunction with Physics-informed models from SPICE (Simulated Program with Integrated Circuit Emphasis) for accomplishing this. Model generalization is attempted by including a Design Factor (Transistor Density) to account for design complexity and Process Factor (using Fab Cp/CpK which is associated with WAT parameter variation) to account for process node.A combined yield metric is proposed which estimates the Total Yield as a function of defect yield and parametric-shift yield by treating them as independent failure events. The yield calculator is further enhanced with a feature for estimating yield loss due to parametric shift. Along with pre-existing Defect-Limited Yield Models the calculator will output the Total Yield based on the combined yield metric.