Transceiver Design for Mobile Networks: Tackling mm-Wave High-Speed Link Challenges and Sub-6GHz Mobile Terminal Blocking Problems
- Author(s): Wang, Huan
- Advisor(s): Heydari, Payam
- et al.
Wireless mobile networks are expected to become progressively more prevalent in the future society, connecting billions of populations across the globe and an even higher number of intelligent devices scattered in the environment. Moreover, the supported data rate on mobile devices keeps increasing with the deployment of next generation network infrastructure, e.g. 5G network, and upgrades on existing infrastructures. Consequently, enormous amounts of data traffic will be generated on a daily basis and data exchange between base stations and the backbone network through conventional backhaul links will quickly become a bottleneck. On the other hand, mobile terminals, the elemental building blocks of all mobile networks continue to be hindered by ever-increasing interference blocking problems in a more and more congested environment, both spectrally and spatially. This dissertation aims to study potential solutions for the aforementioned two major issues in mobile networks from a transceiver circuit design perspective.
In the first part of this dissertation, a direct modulation high-order QAM transmitter architecture is proposed and analyzed for mm-wave high-speed wireless links, targeting for applications such as wireless backhaul. The daunting and costly task of designing integrated
high-speed-resolution digital-to-analog interface and complicated digital back-end in conventional architectures is completely avoided. Link performance, cost and level of integration are greatly improved as a result. Prototype transmitter has been designed, fabricated and
measured to verify the proposed concept. Operating at 115-GHz carrier frequency, the transmitter achieves a 20Gbps data rate in a short-range wireless link using 16QAM modulation. Error vector magnitude (EVM) was measured to be −15.8 dB at a modulated output power of +1 dBm. The transmitter consumes 520 mW of power and occupies 3.17 mm2 of active area in a 180-nm SiGe BiCMOS process.
In the second part, the mobile terminal blocking problem is addressed. While benefiting from superior linearity, blocker-tolerance and high-Q programmable selectivity brought forth by N-path filtering technique, the common problem of elevated local oscillator (LO) leakage in prior work is significantly mitigated in the proposed receiver design to comply with cellular standards. The design of the proposed receiver is analyzed in great details. The prototype receiver was measured to be highly linear with low noise figure and LO leakage. Out-of-band 2nd and 3rd order input-referred-intercept-point (IIP2 and IIP3) reaches +60 dBm and +14 dBm, respectively. Small-signal noise figure was measured to be below 2.5 dB and degrades by 4.5 dB in the presence of a 0 dBm blocker at 80 MHz offset. The LO leakage was kept under −80 dBm up to 2 GHz.