Phase-Locked-Based Phased Array for mm-Wave/Terahertz Radiators
- Author(s): Abedi, Razieh
- Advisor(s): Heydari, Payam
- et al.
Fully integrated implementation of silicon mm-wave/THz radiators and phased arrays is of great interest for various applications such as high data-rate communication, spectroscopy, and imaging. These applications require wide frequency tuning, sufficient radiated power, and variable phase shifting between adjacent sources to perform beam steering. As a result, recent studies have focused on new potentials and existing challenges. The critical issue associated with any system operating at mm-wave/terahertz frequency is a flexible, integrated source providing a sufficient level of power. mm-wave/THz phased array systems demonstrate a potential to overcome the limited available power of transistors close to the maximum oscillation frequency caused by the coherent combining in a phased array. In addition, at mm-wave frequency range, the higher number of these available coherent sources are implemented to compensate for the reduced power of a single source.
Initially the design of a 53-61GHz low-power charge-pump PLL is presented. This integer-N type-II PLL employs a class-D V-band VCO. Transistors in the VCO enter deep triode region to yield low DC power and low phase-noise performance. Pros and cons of the triode region have been studied in this chapter. We have explained how this region has been accurately exploited to improve the phase-noise performance. This is unlike the general notion that the triode region degrades phase-noise performance in oscillators. The PLL is fabricated in a standard 65nm CMOS process. The VCO consumes the minimum power of 10.6mW from 0.8V supply. The PLL achieves a wide tuning range of 13% from 53.35 to 60.83GHz and a phase noise of -88 dBc/Hz at 1MHz offset, while consuming a minimum DC power of 48mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers.
The main challenge of phased-array systems at mm-wave/THz frequency is the design of phase shifters at these frequencies. Passive phase shifters result in undesired power loss. Alternatively, active phase shifters cannot either provide a wide bandwidth with a constant gain or operate in that frequency range. The goal of this study is to achieve a high frequency phased array with stable, controllable, and high accuracy frequency. This is accomplished by combining a PLL with phased array signal generation. This chapter presents a 1x2 PLL-based phased-array radiator operating at 450.4-to- 486.68GHz and 1x2 PLL-based phased-array system operating at 112.66 -to- 121.67GHz. In this work, by utilizing two PLLs, the required phase shift is generated without a need for the separate phase shifting building blocks. Furthermore, this novel topology avoids routing at high frequency which attenuates the signal power and at the same time uses low frequency connections that can be readily scaled to simplify the design. This work is fabricated in a standard 65nm CMOS process and completely scalable to fully exploits advantages of phased-array system.
Finally, a 64-67GHz variable gain attenuator (VGA) is proposed for the amplitude control at each RF channel of a 64-67GHz partially-overlapped phase-amplitude-controlled 4-element beamforming-MIMO receiver. This VGA presents a measured 11dB dynamic range, while exhibiting RMS gain error smaller than 0.32dB within the RF bandwidth. This was achieved by incorporating circuit and EM techniques enabling wide dynamic rang with small gain variation at this frequency range.