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Hardware Trojan Detection in FPGA through Side-Channel Power Analysis and Machine Learning

Creative Commons 'BY' version 4.0 license

The security of a cyber-physical system depends on the safety of the handled data, software, and underlying hardware. Securing the hardware is not a simple task because of the globalization of integrated circuits’ manufacturing flow. One hardware attack to be considered is the modification of the design to insert a “backdoor” which maliciously alters the behavior of the original system. Such a malicious and intentional insertion is called a Hardware Trojan Horse (HTH). In this thesis, an HTH detection technique was proposed and implemented. The detection technique made use of side-channel power analysis along with machine learning to detect the presence of an HTH. Power traces from a golden implementation (HTH-free) of the AES encryption algorithm on an FPGA were used to train a logistic regression model. The obtained model was then tested on new power traces collected from the golden implementation and was able to make correct predictions with 95% accuracy. Next, an HTH, of a few gates, was implemented in the AES circuit to carry out a denial-of-service attack along with a breach of plaintext secrecy. The power data from the HTH-infected circuit were collected and tested on the trained logistic regression model. An amount of 81% of the HTH-infected data was detected as flawed by the logistic regression model allowing the detection of the HTH even when it was not triggered. In fact, even when an HTH was dormant, the HTH would constantly be checking its triggering condition and hence consumed power.

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