UC San Diego

Scientific applications are increasingly using neural networks (NNs) at the edge as a fundamental tool for advancing fields such as particle physics and materials science. As the scientific instruments used in these experiments become more advanced, they produce a lot more data (e.g., 40 TB/s) than before. As a result, scientists are relying on edge NNs, which have more capabilities than traditional algorithms, to process the data. To process data quickly enough, these scientific edge NNS have unique requirements. They must (1) be heavily quantized and (2) execute fully on chip. Even more so, these scientific NNs often operate in high radiation environments (1000× that of space). My thesis focuses on using hardware-software co-design to create efficient, fault-tolerant computer architectures for NNs that execute fully on chip so that they meet the strict latency and throughput requirements laid out by these scientific experiments. I defend the following thesis statement: On-chip neural network inference introduces unique hardware-software codesign challenges and opportunities for building efficient, fault-tolerant neural network architectures. I provide evidence for my thesis in three parts: (1) codesigning residual NNs for efficient inference, (2) scaling up lookup-table NNs, and (3) codesigning fault-tolerant edge NNs. My thesis provides insights and tradeoffs that will help scientists better run their NNs on specialized hardware such as FPGAs and ASICs to advance research in their fields.