UCLA

Living in the era of big-data, it is crucial to store vast amounts of data and process them quickly. Resistive random-access memory (ReRAM) with the crossbar structure is one promising candidate to be used as the next generation non-volatile memory device and is also one essential enabler for accelerators that can drastically increase data processing speed. In this work, we tackle problems in crossbar resistive memory and its accelerator application based on channel coding theory and estimation theory.

In Chapter 2, under the non-negligible device variability in practical resistive memory, we treat the problem of Hamming distance computation between two vectors, using low-level conductance measurement, based on a novel \textit{Computation-in-Memory} architecture, which has shown great potential in reducing the burden of massive data processing by bypassing the communication and memory access bottleneck. We study the feasibility problem of Hamming distance computation in-memory under two distinct sources of memristor variability: resistance variation, and the non-deterministic write process. First, we introduce a technique for estimating the Hamming distance under resistance variation. Then, we propose error-detection and error-correction schemes to deal with the non-ideal write process. These results are then combined to concurrently address both sources of variabilities. Lastly, we demonstrate the efficacy of our approaches on the k-nearest neighbors classifier, a machine learning algorithm that can be accelerated by computing Hamming distance in-memory.

In Chapter 3, considering unreliable selection devices, we study mitigation techniques for the re-occurred sneak-path problem. In a crossbar ReRAM, in which a memristor is positioned on each row-column intersection, the sneak-path problem is one of the main challenges for a reliable readout. The sneak-path problem can be solved with additional selection devices. When some selection devices fail short, the sneak-path problem re-occurs. The re-occurred sneak-path event can be described combinatorially and its adverse effect can be modeled as a parallel interference. Based on a simple pilot construction, we probabilistically characterize the inter-cell dependency of the re-occurred sneak-path events. Utilizing this dependency, we propose adaptive thresholding schemes for resistive memory readout using side information provided by pilot cells. This estimation theoretic approach effectively reduces the bit-error rate while maintaining low redundancy overhead and low complexity.

In Chapter 4, dealing with the increasing resistivity of wordline/bitline in crossbar resistive memory as a result of the scaled down technology node, we propose write/read communication channels under high line resistance and coding theoretic solutions tailored for this channel, targeting the storage class memory (SCM) application. By statistically relating the degraded write/read margins and the channel parameters, we propose binary asymmetric channel (BAC) models for the write/read operations. Method for optimizing the read threshold is proposed to reduce the raw bit-error rate (RBER). Observing a large non-uniformity of reliabilities in the memory array, we propose two schemes for efficient channel coding based on Bose-Chaudhuri-Hocquenghem (BCH) codes. An interleaved coding scheme is proposed to mitigate the non-uniformity of reliability and a location dependent coding framework is proposed to leverage this non-uniformity. Both of our proposed coding schemes effectively reduce the undetected bit-error rate (UBER).