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Towards reliable nanoelectronic systems

Abstract

Nanoelectronics, promising significant boosts in device density, power and performance, has been projected as the new driving force for Moore's law in the post-CMOS era. However, turning the vision of nanoelectronic systems into reality requires solving the fundamental challenge of unreliability. The traditional fault tolerance schemes have focused on low fault rates. Not only do they become impractically expensive, but also they fail to provide the flexibility and resilience necessitated for the significant levels of expected fault rates in the nanoelectronic environment. Furthermore, the particularities of nanofabrics necessitate that the fault tolerance techniques fit certain topological constraints to ensure viability within the expected constraints. Overall, the new realm of nanotechnology imposes manifold challenges on attaining fault resilience. The work in this thesis addresses the reliability challenge in nanoelectronic systems from the following perspectives. Based on a number of new characteristics exhibited in common by the emerging nanoelectronics, a number of peculiar fault tolerance issues are identified and thus focused on throughout the thesis work. First, the two representative genres of fault tolerance approaches, fault masking and online repair, are confronted with unique challenges in nanoelectronic systems. Second, no matter which approach is chosen, building a fault tolerant nanoelectronic system cost-efficiently relies on two main principles: inherent redundancy exploitation, and a hierarchical fault tolerance strategy. Last but not least, the fundamental issue of reliability in nanoelectronics strongly impacts system design, raising a series of new modeling, algorithmic and re-evaluation considerations in the system design perspectives. The success of nanoelectronic system construction essentially relies on the twin approaches of developing aggressive fault tolerance schemes, and novel system design with reliability considerations. The thesis work expands across multiple design abstraction levels of nanoelectronic systems, including a series of fault tolerance approaches that respond to the new characteristics of nanoelectronics, and a number of new system design perspectives that address the reliability challenge

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