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W-band phased array systems using silicon integrated circuits

  • Author(s): Kim, Sang Young
  • et al.
Abstract

This thesis demonstrates the silicon-based on-chip W-band phased array systems. An improved wideband I/Q network to minimize the capacitive loading problem is presented, and its implementation in a 60-80 GHz active phase shifter using 0.13 [mu]m SiGe BiCMOS process is demonstrated. In addition, a 67-78 GHz 4-bit passive phase shifter using low-pass pi-network and 0.13 [mu]m CMOS switches is demonstrated. By adding amplifiers to the passive phase shifter with the architecture of alternating amplifiers and phase shifter cells, a low-power BiCMOS 4-element phased array receiver for 76-84 GHz applications are presented. Lastly, a 76-84 GHz 16-element phased array receiver, designed differentially in order to reduce the sensitivity to packaging effect such as ground inductance, is presented. This thesis presents the silicon-based on- chip W-band phased array systems. An improved quadrature all-pass filter (QAF) and its implementation in 60-80 GHz active phase shifter using 0.13 [mu]m SiGe BiCMOS technology is presented. It is demonstrated that with the inclusion of an Rs/R in the high Q branches of C and L, the sensitivity to the loading capacitance, therefore the I/Q phase and amplitude errors are minimized. This technique is especially suited for wideband millimeter- wave circuits where the loading capacitance (CL) is comparable to the filter capacitance (C). A prototype 60- 80 GHz active phased shifter using the improved QAF is demonstrated. The overall chip size is 1.15 x 0.92 mm² with the power consumption of 108 mW. The measured S₁1 and S₂2 are < -10 dB at 60-80 GHz and 60-73 GHz, respectively. The measured average power gain is 11.0-14.7 dB at 60-79 GHz with the rms gain error of < 1.3 dB at 60-78 GHz for 4 -bit phase states. And the rms phase error is < 9.1° at 60-78.5 GHz showing wideband 4-bit performance. The measured NF is 9-11.6 dB at 63-75 GHz and the measured P₁dB is -27 dBm at 70 GHz. In another project, a 67-78 GHz 4-bit passive phase shifter using 0.13 um CMOS switches is demonstrated. The phase shifter is based on a low-pass pi- network. The chip size is 0.45 x 0.3 mm² without pads and consumes virtually no power. The measured S₁1 and S₂2 is < -10 dB at 67-81 GHz for all 16 phase states. The measured gain of 4-bit phase shifter is -19.2 +/- 3.7 dB at 77 GHz with the rms gain error of < 11.25° at 67-78 GHz. And the measured rms phase error is < 2.5 dB at 67-78 GHz. The measured P1dB is > 8 dBm and the simulated IIP3 is > 22 dBm. A low-power 76--84 GHz 4-element phased array receiver using the designed passive phase shifter is presented. The power consumption is minimized by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and the 11 degree phase shifter are used to correct for the rms gain and phase errors at different operating frequencies. The overall chip size is 2.0 x 2.7 mm² with the current consumption of 18 mA/channel with 1.8 V supply voltage. The measured S₁1 and S²2 is < -10 dB at 70-88 GHz and 74- 88 GHz, respectively. The measured average power gain is 10.1-18.9 dB at 76-84 GHz with the rms gain error of < 0.6 dB at 76-77 GHz, < 0.8 dB at 79-81 GHz and < 1.1 dB at 81- 84 GHz. The measured rms phase error is < 3.9° at 76-77 GHz, < 7.2° at 79-81 GHz and < 10.4° at 81-84 GHz. The measured NF is 10.5 +/- 0.5 dB at 80 GHz and the measured input P1dB is -26.7 dBm to -23 dBm at 77-80 GHz depending on the gain setting. The on-chip coupling is < -30 dB between adjacent channels. Finally, a 76-84 GHz 16-element phased array receiver in a 0.13 [mu]m SiGe BiCMOS process is presented. All circuits are designed differentially to result in less sensitivity to packaging effect and high channel-to-channel isolation. The overall chip size is 5.0 x 5.8 mm� with the power consumption of 500-600 mA from 2 V supply voltage. The measured Sv(1)1 and Sv(2)2 for all 16 phase states is < -9 dB at 72-88 GHz and 73-86 GHz, respectively. And the measured average power gain (Sv(2)v(1)) is > 10 dB for 76.4-90 GHz with the rms gain error of < 1 dB for 74-84.2 GHz. The measured rms phase error is < 11� for 73.6-83.6 GHz. In order to optimize the rms gain and phase errors, the VGA and 11� phase shifter are used. The measured reverse isolation (Sv(1)v(2)) is > -45 dB. The measured NF is 11.2-13 dB at 77-87 GHz at the maximum gain state. And the measured input P1dB is -20 dBm at 77 GHz and -25.8 dBm at the 83 GHz. The measured coupling between channels is < -48 dB because of the relatively high substrate resistance and the long distance between channels

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