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Open Access Publications from the University of California

Design Implementation and Channel Equalization of Double- Edge Pulsewidth Modulation Signaling /


A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to overcome frequency-dependent losses in electrical interconnects. Time domain modulation is discussed as a means to enhance the spectral efficiency in channels with sharp frequency roll-o similar to multilevel voltage-domain modulation such as 4-PAM. The transmitter and receiver are high-speed programmable digital-to-time and time-to-digital converters that adapt to channel bandwidth characteristics with a timing resolution of 40 ps. This thesis presents a low-jitter, phase rotation architecture for cycle-to-cycle transmit pulsewidth control. The transceiver includes an elastic buer to move data between synchronous and plesiochronous clock domains and is implemented in 45-nm CMOS SOI. Transmitter and receiver functionality is demonstrated to 10 Gb/s at a BER of under 10⁻¹² and is compared against NRZ schemes at the same rate. The inductor-less transmitter and receiver active circuitry respectively occupy an area of 93x94 and 218x160 [mu]m², and consume a total 107 mW from a 1.2 V supply. DPWM is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. For the second-generation DPWM transceiver, this thesis presents an 8b/9b line coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buering required in the transmitter and receiver. Furthermore, pre-emphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The second generation DPWM transceiver is also implemented in 45-nm CMOS SOI and operates at 10 Gb/s with 10⁻¹² BER and consumes 94 mW. The power consumption of the 8b/9b coding hardware is 1.5 mW at 10 Gb/s demonstrating low power overhead

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