UC Irvine

In-Memory Computing (IMC) is considered a great candidate to replace the von-Neumann computing architecture to overcome the memory wall. Content Addressable Memories (CAMs) are the main building blocks in IMC-based architectures, such as the associative processors, and they are being used to accelerate machine learning tasks such as inference on Decision Trees (DTs). Decision trees are popular and powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications that have limited power and latency budget. In this paper, we first present a juxtaposition between the capacitive and resistive sensing schemes in 2 Transistor-2 Resistive (2T-2R) Ternary CAMs (TCAMs). A Figure of Merit (FOM), function of the dynamic range, latency, and energy, is defined to have a fair comparison between the two sensing techniques. A mathematical model for the transient behavior of both sensing schemes is derived and verified through SPICE simulations. We then study the performance of the two schemes with an in-memory addition application and the results reveal that resistive sensing has an edge in that context. In addition, we propose a CAM Compiler for DT inference acceleration. In particular, we propose a novel ”adaptive-precision” scheme that results in a compact implementation and enables an efficient bijective mapping to TCAMs while maintaining high inference accuracies. Also, a Resistive-CAM (ReCAM) functional synthesizer is developed for mapping the decision tree to the ReCAM arrays with the capacitive sensing scheme and performing functional simulations for energy, latency, and accuracy evaluations. We study the decision tree accuracy under hardware non-idealities including device defects, manufacturing variability, and input encoding noise. We test our framework on various DT datasets including Give Me Some Credit, Titanic, and COVID-19. Our results reveal up to 42.4% energy savings and up to 17.8x better energy-delay-area product compared to the state-of-art hardware accelerators and up to 333 million decisions per sec for the pipelined implementation.