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Statistical Analysis for On-Chip Power Grid Networks and Interconnects Considering Process Variation
- Mi, Ning
- Advisor(s): Tan, Sheldon X.-D
Abstract
With the aggressive scaling down of semiconductor VLSI devices
from 65nm to 45 nm, 32nm, the process induced variability becomes
the major design concern. The fundamental change in VLSI chip
design in current and future nodes is that what has been designed
will not agree with the products manufactured due to the
uncertainties in the manufacture processes. Even worse, the
variabilities keep growing as the technology scales down
continually. The process induced variations manifest themselves
from wafer to wafer, die-to-die and device to device within a die.
Some are systematic variabilities and some are random
variabilities, which have to leave extra margin for worst case.
The Monte Carlo method can come to the rescue by simulating the
probability of the worst case in a random way. However, it is well
known this approach is very time consuming and forbidding slow. It
is highly desirable to have more efficient statistical modeling
and simulation techniques and tools to guide the design in the
presence of uncertainties in the nanometer VLSI regime.
In this dissertation, the influence of the variability, such as
threshold voltage variation, interconnect wire height, width
variation, on the performance of power grid delivery networks and
signal interconnect circuits, are studied. First we develop a new
statistical method, which is based on concept of Hermite polynomial
chaos, to analyze power grid voltage drop variations of on-chip
power grid networks. The new approach considers both wire
variations and sub-threshold leakage current variations, which are
modeled as lognormal distribution random variables. We also
consider spacial correlation of the leakage variables by applying
orthogonal decomposition to map the correlated random variables
into independent ones before the analysis. Second, we propose a
more efficient statistical analysis approach, StoEKS, in which the
extended Krylov subspace method is used to speedup the solution
procedure of the variational circuit equations. By using the model
order reduction technique, StoEKS partially mitigates circuit-size
increasing problem associated with the augmented matrices from the
Galerkin-based spectral statistical method. Finally, we propose an
efficient method to calculate variational interconnect delay,
which is a crucial step in the statistical static timing
analysis(SSTA). We apply Numerical quadrature method based on
orthogonal polynomial representation (OPR) of statistical
variations to derive the non-linear, non-Gaussian analytic
interconnect delay models in terms of the interconnect wire width,
height variations. It can take in variational parameters in OPR
form and outputs the delays computed in OPR form again, which is
compatible with existing SSTA methods.
Main Content
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