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Analysis and Design of High-Speed CMOS Frequency Dividers

  • Author(s): Molainezhad, Fatemehe
  • Advisor(s): Green, Michael M
  • et al.
Creative Commons Attribution 4.0 International Public License
Abstract

A frequency divider is one of the most fundamental and challenging blocks used in high-speed communication systems. Three high-speed dividers with different topologies, LC-tank frequency divider, CML ring frequency divider, and CML DFF frequency divider with negative feedback, are analyzed based on the locking phenomena. The locking to the injected signal happens as long as the frequency and the amplitude of the injected signal are in the desired operation region of the divider's sensitivity curve. A phase shift (which is a function of both frequency and the amplitude of the injected signal) occurs in the circuit and the divider will be locked to the injected frequency.

Locking to an external signal may not necessarily occur just by considering the frequency of the injection signal being in the locking range, even if the frequency of the injection signal is very close to the self-oscillation frequency in a wide locking range scenario without the proper injected signal amplitude.

To measure the phase shift when the oscillator is locked to the injected frequency, a novel procedure is developed. This procedure gives us a very precise tool to measure the locking phase, instantaneous phase, or the phase between any two signals inside the topology loop and provides a good ability for better understanding of the injection locking concept and the behavior of the divider in the presence of an injected signal. The simulations are using transistor models from TSMC 65nm CMOS process.

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