Strong demand for mm-wave high data-rate links in emerging 5G communication systems has resulted in substantial interest in mm-wave silicon (Si) based radio front-ends. The efficiency of the PA is a significant factor in the overall power dissipation and thermal management of mm-wave transceivers which have arrays with a large number of antennas (RF channels). This dissertation focused mainly on circuit design techniques for cm/mm-wave CMOS power amplifier efficiency improvement at frequencies from 15 GHz to 28 GHz. In addition, a DSP based solution is proposed to increase efficiency and performance of cellular (LTE band) transmitters in the 1-3 GHz frequency range.

For digital communication signals with multi-carrier modulation and high peak-to-average power ratios (PAPRs), high back-off efficiency of the PA is of significant importance. In the first part of the dissertation, possible implementations of linear and efficiency-enhanced CMOS PAs are described. The concept of stacking multiple FETs is applied in the design of symmetric and asymmetric Doherty power amplifiers, as well as compact linear PAs. The dissertation demonstrates that high power density can be achieved with PAs based on 4-stack power devices, while 2-stack devices can be designed to have exceptionally high efficiency due to lower losses. A two stage, high power Doherty PA that uses 4-stack devices in the final stages is demonstrated with more than 25 dBm output power and 25% back-off power added efficiency (PAE) at 6 dB back-off operating in the 15 GHz band. To minimize chip area, the Doherty combiner is based on an optimized, lumped element 90 degrees phase shifter. To overcome the inherent non-linear gain response of Doherty PAs and to minimize the complexity of digital pre-distortion (DPD) due to large channel bandwidth at mm-wave bands, a simple RF domain analog pre-distorter is demonstrated for the first time.

Various compact, linear 2-stack PAs are demonstrated based nMOS and pMOS FETs for saturated output powers in the range of 20 dBm in the Ka-band. Performance and reliability advantages of pMOS based PAs are shown. Also, by using inter-node impedance tuning with a shunt feedback drain-source capacitor, the PAE of the 2-stack PAs is increased even further, resulting in world record 46% PAE for the pMOS PA at 26.5 GHz.

Due to high passive losses in CMOS, achieving high efficiency Doherty PAs requires careful design and non-conventional synthesis methodology for the Doherty combiner. A high efficiency, symmetric Doherty PA for the Ka-band that is based on efficient 2-stack power devices and a low loss Doherty combiner synthesis technique is presented. At 6 dB back-off, the PAE exceeds 28% which corresponds to 1.4x higher PAE than achievable with ideal class B back-off from peak PAE. Such high efficiency is attained due to low combiner losses of 0.5 dB, which is less than half of what can be achieved with a conventional Doherty combiner. Furthermore, an asymmetric Doherty PA is reported that is based on low loss output Doherty combiner and uses a 2-stack cell in the main path and a 4-stack cell in the peaking path, thus improving efficiency at more than 6 dB back-off and achieving high output power. In addition, a compact modeling approach for large, parasitic-extracted PA transistors is presented, which considerably reduces simulation time and accelerates developments of CMOS PAs.

A typical time-division duplex (TDD) transmit/receive (T/R) mm-wave front-end comprises a power amplifier, a low noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this thesis, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure (NF). The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated in CMOS SOI that includes a high power, 4-stack based PA and an inductively source degenerated, cascode based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak PAE of 28%, while the LNA achieves NF of 3.2 dB.

Finally, in frequency division duplex (FDD) systems, spurious emissions from the transmitter (TX) can fall onto the receive (RX) band and lead to significant receiver desensitization. This dissertation proposes a DSP based solution that relies on a linear auxiliary receiver to cancel the RX band noise from the received signal. This technique allows reduction of duplexer rejection requirements in the RX band, and reduction of insertion loss in the TX band, thus, resulting in high PA efficiency and smaller duplexer footprint. PA architectures that inherently have high receive band noise (envelop tracking and digital PAs) can substantially benefit from this technique. More than 22 dB improvement in the signal to noise ratio (SNR) is shown without the presence of desired signal at the antenna.

In order to meet the increasing demand of high data rate mobile broadband communication, newer standards increasingly employ spectrally efficient high order modulation schemes, which lead to large peak-to-average ratio (PAPR) of transmitted signals. To drive down the cost and form factor, a significant portion of the active circuitry in today's commercial handsets is implemented in silicon CMOS technology – except for the power amplifier (PA). Silicon technology comes with low breakdown voltage, however, limiting the output power of the PA. Recent work has shown that series-connection of Si FETs (the "Stacked-FET" technique) can overcome the breakdown issue of silicon CMOS FETs to implement high power PAs. This can enable the use of scaled CMOS technology nodes which are optimized for digital logic circuits, to implement high performance PAs. The PAs, moreover, can make use of the digital circuits available to produce compact integrated circuits that are less dependent on microwave matching techniques than their counterparts. This work investigates the design and implementation of high output power, digitally-intensive PA CMOS architectures and their extensions for wireless transmitters that are highly efficient, even for signals with high peak-to-average ratio.

In the first part of this work, a digitally modulated PA (DPA) is implemented in polar architecture on 180 nm CMOS SOI technology. The amplitude modulation input signal is a 10-bit digital word controlling the number of active unit cells – each unit cell being a stacked FET PA. The DPA is also driven by a constant amplitude phase modulated (PM) signal centered at RF. The demonstrated DPA provides output power of 1.45 W at 900 MHz with drain efficiency of 65.9%. The power and efficiency are adequate for use in cellular handsets for 3G and 4G standards. The DPA can transmit WCDMA and LTE signals at 900 MHz and is functional from 800 MHz to 2.4 GHz with different matching networks. This DPA is a multi-band, multi-standard PA and is used as a building block for additional designs in this work.

The back-off efficiency enhancement of PA is critical to efficiently transmit signals of high PAPR from hand-sets. In the second part of the work, two identical DPAs are used to implement a digitally modulated Doherty power amplifier (DDPA). This part of the work investigates the challenges and develops the techniques for achieving strong efficiency peaking in output power back-off for CMOS Doherty PAs at microwave frequencies. The output combiner needed within the Doherty architecture is realized using surface-mount components on a printed circuit board (PCB). Digital AM signals to both DPAs are independently provided as inputs. The phase difference between RF PM inputs of main and peaking DPAs can also be varied. The peak output power of CMOS DDPA at 900 MHz is >2 W (highest reported in the literature) with drain efficiency of 55.5%, while at 6 dB back-off the drain efficiency is 52.6%. The back-off efficiency and its improvement relative to class-B is highest reported in the literature for any CMOS Doherty implementation. The DDPA is demonstrated to transmit 5 MHz 64-QAM OFDM signal with very good linearity of ACPR better than -35.9 dB and EVM of 3.8%.

For applications like femto-cell base-stations, where the power needed is large, technologies like Gallium Nitride (GaN) work better than silicon because of superior voltage handling. The challenge here lies in efficiently driving the GaN FETs. The DPA developed in this work can provide large enough voltage to directly drive the input of GaN FET, thanks to the use of FET stacking. A novel architecture is demonstrated in which the CMOS DPA drives the GaN FET, which is connected as a common gate stage, with no inter-stage matching. The GaN FET in turn drives a 50 Ω load directly. The absence of any impedance matching network (with its associated bandwidth limitation) makes this PA wideband. Key design aspects of this architecture, including bandwidth limitation caused by circuit parasitics, are discussed in this work. A digitally controlled PA with a combination of CMOS and GaN (Mitsubishi Electric 0.75 μm process) is demonstrated. The CMOS-GaN PA operates over a 2.4:1 frequency range for 1dB output power variation (500 MHz to 1.2 GHz); output power varies from 2.4 W to 3 W with efficiency between 48% to 74%. This PA is demonstrated to transmit 5 MHz, 64 QAM signal at various frequencies. These characteristics make this amplifier a candidate for application in femtocells and microcells.

This dissertation focuses on the development of active load-modulation techniques to improve back-off efficiency of power amplifiers (PAs) while maintaining wide bandwidth and high linearity suitable for modern wireless handsets. High back-off efficiency is required because of the use of high spectral efficiency modulation with high peak-to-average power ratio (PAPR), which causes the PA to operate in a back-off condition most of the time, typically reducing the efficiency. The Doherty architecture is a widespread active load modulation technique. A well-known issue for Doherty PAs, however, is limited bandwidth due to the use of frequency-sensitive quarter-wave transmission line or its equivalent as impedance inverter. In this work, the impedance inverter is eliminated by using voltage-source PA building blocks, rather than current-source PAs used in conventional Doherty PAs. Such idea was shown in Doherty’s original paper (1936), however it was long forgotten due to the unavailability of voltage-source PAs. Mainstream Doherty amplifiers are implemented using two current source PAs and an impedance inverter. Recently, advances in CMOS devices and PA architecture have led to a high efficiency, high linearity voltage source PA, a switched capacitor power amplifier (SCPA). In this dissertation, a Doherty PA without impedance inverter, the Voltage-Mode Doherty (VMD), is realized by using SCPA building blocks. The VMD is fabricated in 65nm CMOS and achieves 24dBm saturated power (Psat) with power-added efficiency (PAE) of 45%/34% at 0dB/5.6dB back-off, comparable to the state of the art however with much wider 1dB fractional bandwidth from 750MHz to 1050MHz. With memoryless linearization, the VMD transmits 40MHz 256-QAM 802.11ac modulation with -34.8dB EVM and 22% PAE. Compared to the state of the art, the VMD achieves much better modulation accuracy with similar PAE. The wide bandwidth, high back-off efficiency, and excellent linearity of VMD architecture enable high efficiency RF transmitters for future wideband and high spectral efficiency modulation.

Another issue of commonly used active load modulation techniques is a rather “shallow” back-off efficiency enhancement of about 6dB. Since modern modulation signals have PAPR of about 10dB, achieving deeper back-off enhancement can further improve the overall efficiency. Several hybrid architectures have been demonstrated to have efficiency enhancement beyond 6dB back-off. However, they come at the cost of a mode-switching glitch which occurs when the PA changes configuration. The mode-switching glitch causes increased distortion in the transmitted signal proportional to the modulation bandwidth, thus preventing these PAs to be used with future wideband modulation. The second part of the dissertation combined the class-G SCPA and VMD used in the first part of the dissertation to implement a PA with efficiency enhancement up to 12dB back-off without mode-switching glitch. The CG-VMD PA is fabricated in 45nm CMOS SOI with integrated balun. At 3.5GHz, it achieved 25.3dBm Psat and 30.4%/25.3%/17.4% PAE at 0/6/12 dB back-off, comparable to the state of the art with much wider bandwidth of 1GHz. With memoryless linearization, the PA achieved 19.2% PAE with −35.8dB EVM while transmitting a 40MHz 256QAM 10.1dB PAPR 802.11ac modulation. The excellent achieved EVM is superior to what is achieved in current state of the art hybrid architecture due to the absence of mode-switching glitch.

The third part of the dissertation investigates the distortion caused by the mode-switching glitch in dynamic reconfiguration PAs, and compares it to the glitch-free technique developed in this dissertation. The PA described above provides sufficient flexibility that with software control it can be used to create a mode-switching discontinuity in the same way as the power-combined transformer reconfiguration architecture used in several recent high efficiency PA reports. The measured results show a significant glitch in the signal envelope when the mode-switching occurs, causing both in-band and out-of-band distortion. A correction technique was developed to partially correct the distortion caused by the glitch. It is shown, however, that the in-band distortion can be corrected at the cost of increased out-of-band distortion. With optimal operation of the PA demonstrated in the dissertation, no glitch is observed in the signal envelope, and in-band and out-of-band distortion are much improved. This result quantitatively demonstrates the benefits of the VMD and CG-VMD glitch-free architectures for future wideband high spectral efficiency modulation.

The emerging 5G and mm-wave high data rate wireless communication applications have exacerbated the challenges of the PA design, especially for the commercial Si-based ICs. The complex wideband OFDM signals in these applications, with high PAPR, demand stringent PA requirements of linearity, and efficiency at both peak and backoff power levels. This dissertation addresses the design challenges for sub-6GHz and 28GHz CMOS and SiGe integrated PAs, by introducing novel techniques and presenting them with proper mathematical framework and modeling, alongside the hardware implementations that achieve record results.

Active load modulation, employed in Doherty and Chireix outphasing architectures, is one of the well-known techniques to improve the backoff efficiency of PAs. In theory, outphasing offers a better efficiency profile than Doherty, but it was traditionally believed that it works well only with voltage-mode PAs. However, recently it has been shown that for outphasing with current-mode PAs, if the input drive power reduced at backoff, good results can be achieved. In this dissertation a detailed mathematical analysis for current-mode outphasing is presented, and then the implemented 5.5GHz 45nm CMOS-SOI dual-input outphasing PA is discussed that achieves record average PAE of 30.9% while generating a 40MHz 64-QAM OFDM modulated signal with 7.9dB PAPR and 14dBm average output power.

At 28GHz band, the loss due to the integrated passive elements is one of the bottlenecks to achieve high efficiency. To address this issue a novel Chiriex combiner based on a “triaxial balun” is presented. An equivalent circuit model of the balun is introduced for the first time to make the analysis and design more straight forward. The implemented chip in 130nm SiGe BiCMOS process shows balun loss of only 0.5dB at 28GHz, and the dual-input outphasing PA achieves a record average PAE of 25.3% for an 8.1dB PAPR, 80MHz 64-QAM OFDM signal with average output power of 14.3dBm.

In phased array systems, it is not practical to employ individual digital predistortion (DPD) for each PA unit, and they must be inherently linear. A novel architecture named Single Input Linear Chireix (SILC) PA is introduced that not only has a high backoff efficiency but also has a linear response achieved by correcting the transistor related distortions using the systematic AM-AM and AM-PM variations. The implemented PA in 130nm SiGe process demonstrates 19dBm saturated output power with 34.4% peak PAE and 6-dB backoff PAE of >23% at 27.5GHz. The modulated signal performance using a 100MHz 64-QAM OFDM signal shows average output power of 11.9dBm with PAE >20%, EVM <5%, and ACLR<-33dBc without using predistortion.

For 28GHz applications that require small footprint, the 2-stack CMOS PAs can offer enough output power with high peak efficiency. In order to improve the linearity, it is desirable to design for a “sweet spot” in the 3rd order intermodulation (IM3) at a critical power, where the distortion is significantly decreased. By adding a large resistor with a proper value at the gate of the transistor, the power dependent leakage current is used to create a dynamic bias that results in a slight amount of gain expansion that counters the gain compression due to the saturation of the PA. Experimental result using a 2-stack 28GHz PA implemented with 45nm CMOS-SOI shows peak output power of 19dBm and 43% PAE, and can attain high linearity without predistortion. Two-tone measurements show the formation of sweet spots at which IM3 decreases on order of 5-10dB at output power levels of order of 5dB backed off from P1dB.

To integrate SiGe into future CMOS devices, it is essential to realize reliable strategies to deposit very thin high-k dielectrics on SiGe surfaces with a low density of interfacial defects. HfO2 was deposited by atomic layer deposition (ALD) using HfCl4 and H2O precursors. The quality of interfaces was varied by ex-situ surface treatment prior to ALD, including HF clean and HF clean followed by wet ammonium sulfide treatment. Electrical properties of the interfaces were examined by variable frequency capacitance-voltage (C-V) spectroscopy. Interfaces passivated by sulfur were found to have nearly 2x smaller density of interface traps than HF-treated interfaces, particularly near the edge of the valence band. The effect of Pd/Ti/TiN as a gettering gate electrode on the electrical characteristics of the interfaces were compared with Ni. By using Pd/Ti/TiN gate electrodes, lower equivalent oxide thicknesses (EOT) were achieved, but no significant improvement in the interface quality was observed.

This dissertation discusses various physical aspects of graphene electronic devices, particularly FETs, of importance for high frequency (RF, microwave and mm-wave) applications. Device physics of graphene junctions and contact junctions are considered. Inhomogeneity effects, heat dissipation and graphene FET compact modeling including unique nonlinearity mechanisms are discussed.

The first part of the dissertation discusses device physics of graphene. The importance of its unique band structure, high carrier mobilities, and maximum current handling are highlighted for RF applications. Graphene junctions are discussed in detail, including p-n junctions and graphene-to-metal junctions. It is shown that graphene p-n junctions provide additional resistance at the transition region within representative FETs due to depletion of carriers, which results in asymmetric ambipolar Id-Vg curves. It is also shown that a charge transfer region is formed at metal-graphene edges, which produces errors in the customary contact resistance measurement and analysis. Both junction effects are controlled by carrier density of the film, fringe electric field, and bias conditions.

Inhomogeneous graphene films are modeled in detail to describe the formation of electron-hole puddles, and their impact on Hall mobility measurements. Inhomogeneity is more significant with larger amplitude of random charge fluctuation and the size of puddles. It is shown that measured Hall mobility can be degraded by more than 8 % due to inhomogeneity, compared with ideally uniform films with the same average carrier density.

Thermal properties of graphene FETs must also be understood in relation to their performance and reliability. Heat dissipation of graphene devices has been analyzed with 3-D thermal simulations. The significance of interface thermal resistance, device design for quick heat release, and contact metal use for lateral heat spreading is described. Simulation and experimental results showed that pulses as short as 200 ns can still heat up graphene devices due to their small heat capacity.

Finally, graphene device models are developed in two forms: a SPICE-like compact model for straightforward usage in circuit simulators, and a more abstract analytic model for investigation of the impact of device parameters on circuit performance. Both device models are used to explore the performance of graphene-based FETs in zero bias r.f. power detector and resistive linear mixer applications. Parasitic elements such as parasitic capacitances, gate and series resistances are included for realistic circuit simulation, and the role of these components on the circuit performance is investigated. Graphene-based zero-biased power detectors showed sensitivity comparable to those using CMOS and InP HEMT-based technologies. Simulated noise equivalent power (NEP) was estimated to be as low as 10 pW/Hz0.5 for a passive r.f. power detector, thanks to the suppression of flicker noise. The mixer also exhibited linearity comparable to state-of-the-art, with input third-order intercept point (IIP3) estimated at about 22 dBm. Simulation results describe the experimental results well. The impact of different device design parameters are investigated by simulation in order to optimize performance.

With the scaling of MOSFET devices down to the sub-10 nm regime, there has been an active search for novel designs and device physics for lower $V_{DD}$ operation. For MOSFETs, the theoretical limit of 60mV/dec sub-threshold slope has posed a lower limit for $V_{th}$ below which leakage current in OFF-state is undesirably high for digital circuit applications and consequently a limit for supply voltage $V_{DD}$ . What's more, short channel effects such as drain induced barrier lowering (DIBL) has also been a challenge for every iteration of technology node below 100nm. Tunnel field effect transistor, a design that utilizes band-to-band tunneling (BTBT), becomes a promising candidate because of its capability in achieving sub-60mV/dec, more resistance to short channel effects and less temperature dependent characteristics, especially in OFF-state.

This thesis focuses on the modeling of tunnel FETs in a variety of aspects, including analytic modeling; temperature dependent factors and physical noise analysis of double gate tunnel FET structures; and compact modeling and physical analysis of vertical tunnel field effect transistors with a distributed circuit model.

In the analytic modeling of double gate TFET work, an analytic tunnel barrier model for TFET is formed by solving a 2D homogeneous Poisson equation. The approximate solution, an exponential function for long channel barrier and a $sinh$ function for short channel barrier, is proposed to replace the Kane's tunnel model, which assumes a constant field and homo-junction for tunneling. Tunneling probabilities are thus evaluated analytically for exponential barrier conditions, and current density is integrated numerically. Furthermore, short channel effect, source doping effect, debiasing effect (which details how the carriers accumulated in the channel affect the potential profile in the linear region), and dimensionality dependence (dimension of density of states) are further studied starting from the analytic expressions of tunnel barriers. The model shows much higher computational efficacy than the Sentaurus TCAD simulator and higher accuracy than a simple Kane model.

TFET is also desirable for the weak dependence of BTBT mechanism on temperature. Yet, there are other temperature dependent factors affecting the performance of TFET such as threshold voltage shift and effective tunnel gap shrinking. In this work, several possible temperature dependent factors that are intrinsic in semiconductors are studied for a double gate TFET, and their effects on $V_{th}$ and tunneling bandgap $E_g^{tun}$ are elaborated. These factors include bandgap shrinkage, temperature dependent Fermi-Dirac distribution in source region (source degeneracy) and temperature dependent effective DOS mass in the channel (which determines quantum confinement). It is found that there are canceling effects between quantum confinement, source degeneracy with bandgap shrinkage in $V_{th}$ calculation as well as tunnelling bandgap calculation. The canceling effects result in a weak dependence on temperature of both threshold voltage (affecting $I_{off}$) and tunnel bandgap (affecting $I_{on}$). One can further optimize the temperature dependence and ON-state current by tuning the device thickness. Trap-assisted tunneling (TAT), a temperature dependent extrinsic effect, is further simulated from a more practical standpoint. It is found that the TAT will mostly affect the current leakage floor rather than degrading the sub-threshold slope in a full current range.

Noise model is an essential for many circuit design simulations. To develop a noise model for a TFET involves different noise mechanisms and physics from the case for a MOSFET. In this work, frequency independent noise (white noise) and frequency dependent noise (flicker noise) are considered for a double gate TFET. For white noise calculation, both shot noise at the tunnel junction and thermal noise in the channel are considered for a device with 100nm gate length. Their individual contributions to drain terminal current are calculated using the impedance field method. As for flicker noise calculation, it is found from number and mobility fluctuation models aided by Sentaurus simulation that the most significant noise contribution originates near the tunnel junction in the saturation region of the $I-V$ curves, and mobility fluctuations become nontrivial in the linear region.

Finally, a novel structure where tunneling happens between two layers in a direction orthogonal to the source-to-drain net current flow direction ("vertical TFET") is studied using a distributed circuit model. Both vertical tunneling and lateral drift-diffusion model are considered in the overall calculation and the competitions between these two mechanisms are shown. A shorter gate length increases the conductivity in the lateral direction, but decreases the conductivity in the vertical direction. Therefore, there exists an optimized gate length for DC ON-current density. However, in terms of RF performance, it is found that shrinking the gate length boosts the cut-off frequency and the speed of transistors because of a major reduction in capacitance with little accompanying decrease of transconductance. Finally, parasitic elements are considered for more realistic RF modeling.

This dissertation has been mainly focused on reconfigurable mm-wave integrated circuits for next generation wireless communication systems (namely, 5G). One of the major approaches to making 5G a reality is the use of high-frequency signals in the millimeter-wave (mm-wave) frequency band to facilitate access to more bandwidth. This can deliver faster and more reliable data to more users. This dissertation contributes to making wideband, bidirectional, and scalable RFICs for high data rate point-to-point communications over large distances in mm-wave bands, particularly the E-band (71-76 GHz, 81-86 GHz). The E-band is a licensed band in the US, with 10 GHz of bandwidth allocated to low-cost, high-capacity, and point-to-point communication. For backhaul base-stations or air-to-ground communication, a scalable and large-element phased array is desired to acquire the appropriate isotropic radiated power and signal to noise ratio. Additionally, bidirectional operation supporting transmit (TX) and receive (RX) in a single aperture is desirable to minimize the area and save power. This dissertation has focused on new architectures for scalable, bidirectional, and wideband phased arrays using IBM's fastest SiGe technology, 90 nm.

In this dissertation, the first E-band scalable phased-array transceiver is proposed based on coupled oscillator architecture. Coupled oscillator phased arrays have the advantage of low power and low complexity, resulting in an architecture that easily scales to the number of elements as multiple die can be aggregated to form a larger array through local oscillator (LO) power distribution and intermediate frequency (IF) power combining. However, silicon processes introduce undesirable parasitics and manufacturing tolerances to the transistor and passive devices. When multiple oscillators are present in a single die, the oscillators couple through the substrate. The substrate coupling introduces additional parasitic coupling paths between oscillators; this causes pulling and, consequently, amplitude and phase variation between the oscillators. In addition, the parasitics from the injection node to the substrate deviate the ILO performance from its ideal behavior. Conventional analysis of the amplitude and phase noise typically ignores the effect of the silicon substrate parasitic effects.

This dissertation investigated the nonlinear dynamics of an injection-locked oscillator (ILO), where the effective circuit parameters of ILO performance were observed. More specifically, new amplitude and phase equations are derived that took into account the transistor's device parasitics and silicon substrate's parasitic coupling effects, including the transistor injection node parasitic capacitance ($C_{P}$), substrate parasitic conductive ($R_{sub}$) and dielectric ($C_{j}$) features. The derived models are compared with both the simulation and measurement results.

The proposed 2x2 transceiver phased array block diagram described in this dissertation employs 4 injection-locked oscillators (ILOs) operating at a lower frequency range (in this case, 1/4 of the desired LO frequency), followed by a frequency quadrupler, to form a beam in transmit and receive modes. The bidirectional front-end is designed to operate at E-band within 3-dB bandwidth. Since the ILO-based phase shifting is technically challenging at millimeter-wave bands due to the parasitics of the injection circuitry and the oscillator phase noise trade-offs, the high-frequency limitations of the ILO phase shifter is considered and wide locking range and a less parasitic sensitive solution for current injection using folded-cascode architecture is proposed. The proposed ILO-based phase array architecture result in low phase noise and low channel to channel isolation supporting 6 Gb/s data rate at 256 QAM modulation.

The conventional architectures of the E-band transceiver require a wide tuning range, around 10 GHz, for the LO signal and wide-bandwidth IF blocks. The wide-bandwidth requirement of LO and IF frequency for mm-waves increases the power consumption and complexity of the system. This dissertation proposes a novel architecture, named the "Image-selection" E-band phased array. This new architecture makes the upper-band (81-86 GHz) and the lower-band (71-76 GHz) of the E-band spectrum images of each other in comparison to the LO signal, which is located at the center frequency (78.5 GHz). Therefore, an image rejection architecture is desired to select the wanted band while rejecting the other. The significant advantage of this architecture is that it only requires an LO with the quadrature phases within a tuning range lower than 1 GHz . This will relax the system design trade-offs to the circuit impairments. For bidirectional operation purpose and preventing use of quadrature generation circuitry at direct intermediate frequency (IF) or radio frequency (RF) signal paths, sliding-IF weaver architecture mixers are employed with the phase inverter in the divider path to select the upper or lower band. This architecture leads in to a flat conversion gain over the bandwidth and low amplitude and phase imbalance. The achieved QAM modulation data rate from this technique is the state of art,\lyxdeleted{najmebi}{Mon May 29 19:43:48 2017}{ } 9Gb/s (64 QAM) with less than 5% EVM and 12 Gb/s (16 QAM) with less than 10% EVM.

Emerging millimeter-wave applications, including high speed wireless communication using 5G standards, favor silicon technologies, both CMOS and SiGe, for transceiver design, due to the high level of integration at reduced cost and availability of high speed transistors. Efficient, linear and reliable high power amplifiers with broad bandwidth are needed at the transmitter front-ends to enable high data rate links at long distances. But the low breakdown voltage of CMOS FETs due to gate length scaling and other transistor non-idealities make the design of high power mm-wave amplifiers in deeply scaled CMOS nodes difficult. Circuit techniques like FET stacking provide a compact and efficient way of implementing high power mm-wave amplifiers reliably. Other power combining techniques such as on-chip and spatial power combining can be used along with FET stacking to achieve even higher output power levels. This thesis investigates the design of high power mm-wave power amplifiers at frequencies from 28 GHz to 94 GHz, using multiple power combining techniques.

This work extends the use of FET stacking for high power PA design to 94 GHz. A 3-stack PA designed in 45 nm CMOS SOI with 17 dBm output power and 9% efficiency is presented. Using this PA as front-end, a CMOS PA-antenna array is designed, to additionally provide spatial power combining. The CMOS chip has a 2 x 4 array of pseudo-differential power amplifiers along with the signal distribution networks and pre-drivers. A quartz wafer with a 2 x 4 array of differential microstrip antennas deposited on it is placed on top of the CMOS chip, electromagnetically coupled to the PA outputs on the CMOS chip. The spatially power combined PA-antenna array achieved a measured equivalent isotropic radiated power (EIRP) of 33 dBm and an estimated output power of 24 dBm at 94 GHz. Modulated data measurements at 3 Gbps (375 MS/s, 256 QAM) speed using digital pre-distortion are demonstrated with the PA-antenna array.

A novel layout style is introduced for stacked FET design at low mm-wave frequencies. A small multi-finger FET is laid out with fingers connected in series to create the stacked FET. The gate capacitors are realized around the FET with the back-end-of-line metal available in the CMOS process. Multiple multigate cells are interconnected to implement the stacked FET PA. A PA designed in this style in 45 nm CMOS SOI process achieved 24.8 dBm of output power and 29% PAE at 28 GHz with high reliability. This PA is very broadband and linear as shown by the modulated data measurements achieving a data rate of 36 Gbps (6 GS/s, 64 QAM) at 14 dBm with 9.3% PAE, with no digital predistortion.

NFETs and PFETs available in nano-scale CMOS processes are compared and it is shown that in deeply scaled processes, PMOS devices are a viable alternative to NFETs due to their cut-off frequencies similar to those of NFETs, and higher breakdown voltages than NFETs. The first exclusively PMOS mm-wave PA design is reported. This 3-stack PA, made in 32 nm CMOS SOI process, achieved a maximum output power of 19.6 dBm and maximum efficiency of 24% at 78 GHz.

All the designs reported in this thesis achieved either the highest output power or the highest PAE for a CMOS PA at their respective frequencies.

An electrochemical cell is an energy storage device that involves both electrons and ions as part of the storage mechanism. In this work, we investigate the use of nanostructures on the electrodes of the cell to increase the active surface area, and the consequent quantum effects introduced to the cell. With regards to capacitive storage, we predict quantum capacitance will affect the storage capacity of electrons on the electrode, and limit the increase in total capacitance of the device from scaling with the increase in active surface area. Furthermore, we predict geometric effects will affect the screening ability of ions in the electrolyte, allowing device current during charge/discharge cycles to be higher than for a flat electrode. With regards to battery-like storage, we predict the density of states of the electrode will affect the device current, possibly increasing device currents for higher overpotentials compared to a flat electrode battery. This last prediction is based on treatment of the redox reaction process as a tunneling process between electron and ion, akin to a recombination process between electron and hole in a solid state device such as a reverse biased diode.