This report examines ultra-fine grain machine parallelism determined by various hardware styles and constraints. Two major components are incorporated in our system: (1) A generalized parameterized architecture model which characterizes different design styles and constraints based on parallel pipelined machines. (2) A retargetable compiler which maps instruction parallelism to ultra-fine grain machine parallelism for target architectures. Basically the generalized parameterized model is used to specify different target machines, and the retargetable compiler compiles and schedules applications, codes written in high-level language, into control codes for given target machines. The resulting control codes are run through a simulator, after which dynamic statistics of the execution are recorded and the ultra-fine grain parallelism of target machines is assessed. A set of studies has been conducted to demonstrate how ultra-fine grain machine parallelism is affected by various hardware parameters and how performance is affected by both instruction parallelism and machine parallelism.

Partitioning a system's functionality among interacting hardware and software components is an important part of system design. We introduce a new partitioning algorithm that caters to the main objective of the hardware/software partitioning problem, i.e. minimizing hardware for given performance constraints. We demonstrate results superior to those of previously published algorithms in tended for hardware/software partitioning.

Hardware-software codesign, which implements a given specification with a set of system components such as ASICs and processors, includes several key tasks such as system component allocation, functional partitioning, quality metrics estimation, and model refinement. In this work, we focus on the model refinement task which transforms a specification from an original functional model to a refined implementation model. First, we categorize several commonly-used implementation models and describe a set of refinement procedures to transform a specification to each of these implementation models. We also present a set of experimental results to compare the implementation models and to demonstrate how the proposed approach can be used to explore different implementation styles.

Previous work in software/hardware codesign has addressed issues in system modeling, partitioning, and mixed module simulation and integration. Software estimation, which provides software metrics to assist the software/hardware partitioning, has not been studied. In order to rapidly explore large design space encountered in software/hardware systems, automatic software estimation is indispensable in software/hardware partitioning in which designers or partitioning tools must trade off a hardware with a software implementation for the whole or a part of the system under design. In this report we present a software estimator that provides three software metrics --- execution time, program-memory size and data-memory size for a specific executing on a given processor. Experiments have shown that our estimator has less than 20% estimation errors on different designs spanning from straight line code to code with branches and loops and even to hierarchical specifications. Experiments also show that our estimator is fast and can provide rapid feedback to the designers or partitioning tools to quickly evaluate different design alternatives.

This report describes a presentation on the design methodology and the user's view of the SpecSyn system design framework. Given an abstract specification of a system, we present specification capture and the subsequent refinements that will result in the synthesizable descriptions. The advantages of the underlying methodology compared to current approaches are highlighted.

In this report we present two appraoches for synthesis of real-time systems with a minimal number of application specific integrated circuits (ASICs) while still meeting the required performance constraints. One approach starts with a single process description which can be easily compiled into a software implementation for any standard processor. If this software implementation does not satisfy the required performance, descriptions of the performance-critical parts are extracted out and implemented as ASICs. The other approach starts with a description written as multiple processes communicating through global signals. The description can be naturally mapped to a hardware-only implementation in which each process is implemented as one ASIC. In order to minimize number of ASICs, the processes are merged and split for mapping to a combination of standard processors and ASICs. The step-wise refinement process for both approaches is demonstrated on an example of a real-time system. Issues and tools regarding the automation of the proposed codesign methodology are also discussed.