Matrix computations lie at the heart of many scientific computational algorithms including signal processing, computer vision and financial computations. Since matrix computation algorithms are expensive computational tasks, hardware implementations of these algorithms requires substantial time and effort. There is an increasing demand for a domain specific tool for matrix computation algorithms which provides fast and highly efficient hardware production. This thesis presents GUSTO, a novel hardware design tool that provides a push-button transition from high level specification for matrix computation algorithms to hardware description language. GUSTO employs a novel top-to-bottom design methodology to generate correct-by-construction and cycle-accurate application specific architectures. The top-to-bottom design methodology provides simplicity (through the use of a simple tool chain and programming model), flexibility (through the use of different languages, e.g. C/MATLAB, as a high level specification and different parameterization options), scalability (through the ability to handle complex algorithms) and performance (through the use of our novel trimming optimization using a simulate & eliminate method providing results that are similar to these in commercial tools). Although matrix computations are inherently parallel, the algorithms and commercial software tools to exploit parallel processing are still in their infancy. Therefore, GUSTO also provides the ability to divide the given matrix computation algorithms into smaller processing elements providing architectures that are small in area and highly optimized for throughput. These processing elements are then instantiated with hierarchical datapaths in a multi-core fashion. The different design methods and parameterization options that are provided by GUSTO enable the user to study area and performance tradeoffs over a large number of different architectures and find the optimum architecture for the desired objective. GUSTO provides the ability to prototype hardware systems in minutes rather than days or weeks

We present a novel scalable architecture for matrix inversion that uses the modified Gram-Schmidt algorithm based on QR decomposition. Our core achieves a throughput of 0.18M updates per second for a 4 x 4 matrix using 19 bits of precision on a Xilinx Virtex4 SX FPGA. We also present two different designs which use longer data lines, 26 and 32 bits, and compare our results with another matrix inversion architecture which is the only scalable approach so far. We show that our core is significantly faster than the other published FPGA implementation as it requires fewer resources due to the usage of fixed point arithmetic and an effective resource utilization. We show that our proposed architecture is scalable by presenting the results for 6 x 6 and 8 x 8 matrices.

Pre-2018 CSE ID: CS2009-0938

We present a novel architecture for adaptive weight calculation (AWC) that uses the QR decomposition based recursive least squares (RLS) algorithm. Our AWC core achieves a throughput of 0.20M updates per second for a 4 x 4 matrix on a Xilinx Virtex4 SX FPGA. We show that our core is significantly faster than other published FPGA implementations and it requires fewer resources. This is largely a consequence of careful error analysis that allows us to take advantage of a fixed point data representation with little degradation in the final results. Finally, our proposed architecture scales well for larger size matrices.

Pre-2018 CSE ID: CS2009-0937

Matrix computations such as matrix decomposition and inversion are essential for various algorithms which are employed in wireless communication. FPGAs are ideal platforms for such applications; however, the need for vast amounts of customization throughout the design process of a matrix computation core can overwhelm the designer. This paper presents an automatic generation and optimization methodology for different matrix computation architectures using a generator tool, GUSTO, that we developed to enable easy design space exploration with different parameterization options. We especially concentrate on wireless communication MIMO-OFDM applications which often use small matrix dimensions. We present automatic generation of a variety of general purpose matrix computation architectures and optimized application specific architectures. GUSTO’s application specific architectures have comparable results to published architectural implementations, but offer the advantage of providing the designer the ability to study the tradeoffs between architectures with different design parameters.

Pre-2018 CSE ID: CS2009-0936