UC Santa Barbara

Abstract--- This dissertation describes a design and analysis methodology for \Sigma\Delta bitstream filters and controllers in digital hardware. These circuits emulate continuous linear time invariant (LTI) models and directly process \Sigma\Delta encoded bitstreams produced by \Sigma\Delta-based data converters. Since these converters are oversampled, there is a natural opportunity for clocking at the oversampling rate allowing for multiplierless, low latency designs. Direct processing of bitstreams also eliminates lowpass filtering and decimation necessary for conventional bit-parallel DSP. Combined, these changes reduce the hardware resources by more than an order of magnitude in FPGA implementations, with similar improvements in power overhead. MASH techniques (used extensively in data converters) are developed to allow for substantive improvement in resolution or reduction of the oversampling rate. These results have very substantive implications in the design of low-complexity, high performance controllers. In particular, these techniques can obviate conventional DSP augmented designs allowing for robust control in applications unreachable with current technology.