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Interposer-Based ESD Protection: A Potential Solution for μ-Packaging Reliability of 3D Chips

Published Web Location

https://doi.org/10.3390/mi16040488
Abstract

The ending of Moore's Law calls for innovations in integrated circuit (IC) technologies and chip designs. Heterogeneous integration (HI) emerges as a pathway towards smart future chips for more Moore time and for beyond-Moore time, featuring systems-on-integrated-chiplets (SoICs) and advanced micro-packaging (μ-packaging). Reliability, particularly with regard to electrostatic charge (ESD) failure, is a major challenge for 3D SoIC chips in μ-packaging, which is an emerging design-for-reliability challenge for future chips. This perspective article articulates that interposer-based ESD protection will be an important potential solution for 3D SoIC chips in μ-packaging against the devastating ESD failure problem.

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