UC Irvine

Targeting the next generation of AI accelerators, FlexiBit has been proposed as a fully flexible-precision, bit-parallel architecture that efficiently supports both floating-point and integer arithmetic in arbitrary precisions and formats. By enabling true bit-parallel execution for any bitwidth—rather than relying on temporal bit-serial techniques—FlexiBit eliminates compute-unit underutilization and delivers substantial performance-and-area gains. Building on the FlexiBit foundation, this thesis presents a Hybrid Bit-parallel and Bit-serial Processing Architecture that delivers dynamic precision and performance scalability under tight area and energy constraints. This thesis design a dual-mode processing element that can operate in a wide, low-latency parallel mode or a narrow, energy-efficient serial mode, and rapidly switch between them at runtime. Across precisions from 1 to 64 bits, we systematically measure area, latency, and energy to characterize the full design space. Furthermore, we introduce a word-sliced scheme—partitioning an N-bit operand into K slices of P bits—to interpolate between pure parallel and pure serial extremes. Our results demonstrate that hybrid configurations can achieve near-parallel throughput with area and energy costs approaching those of purely serial designs, offering a practical, adaptable accelerator solution for AI workloads with varying accuracy and efficiency requirements.