Holey Silicon and Through Silicon Vias for Thermal Management of Next-Generation Electronic Systems
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Holey Silicon and Through Silicon Vias for Thermal Management of Next-Generation Electronic Systems


The trends of electronic systems toward nanoscale, high power, and 3D integration have made heat dissipation from local hot spots to heat sink structures ever more challenging. Meanwhile, recent advances in fabrication and manufacturing technologies have enabled the development of unique structures and brought new opportunities to address thermal management challenges. This doctoral research focuses on the use of holey silicon and through silicon vias to provide device-level and system-level cooling solutions for next-generation electronic systems.Lateral thermoelectric coolers where Peltier cooling and heating occur in the lateral direction offer solid-state hot spot cooling capability. While most advanced thermoelectric materials with low thermal conductivities provide necessary temperature gradients for thermoelectric conversion, the heat generation in electronics is detrimental to the system where high thermal conductivity is preferred. The contrasting needs of thermal conductivity are evident in thermoelectric cooling systems which call for a fundamental breakthrough. In this dissertation, we show a silicon nanostructure with vertically etched holes, or holey silicon, uniquely combines low thermal conductivity in the in-plane direction and high thermal conductivity in the cross-plane direction, and this anisotropy is ideal for lateral thermoelectric devices. The low in-plane thermal conductivity due to substantial phonon boundary scattering in small necks sustains temperature gradients for the Peltier effect. The high thermal conductivity in the cross-plane direction due to persistent long wavelength phonons effectively dissipates heat from a hot spot to the heat sink structure. Furthermore, cooling performance of holey silicon-based thermoelectric coolers can be significantly enhanced by integrating a metallic through silicon via that directly draws heat from a hot spot. Beyond the steady-state operation, we demonstrate a transient supercooling effect, driven by the temporal and spatial interplays between the interfacial Peltier effect and the volumetric Joule heating effect. Holey silicon with anisotropic thermal conductivity is favorable by delaying the heat diffusion in the lateral direction while allowing rapid heat dissipation in the vertical direction. The transient cooling performance can be further improved by incorporating phase change materials within holey silicon, in which their melting process delays the temperature overshoot. Apart from simulations, we fabricate holey silicon-based thermoelectric coolers through standard semiconductor processes and experimentally demonstrate their cooling performance through an infrared thermography-based measurement. The cooler temperature reduction can be improved by increasing the operating temperature. Transient supercooling is also achieved by applying a current pulse, where the cooler temperature can be temporarily lower than the minimum value in steady state. While lateral thermoelectric devices provide extraordinary device-level cooling performance, the recent development of three-dimensional integrated circuits demanding system-level cooling solutions to advance processor design and enable continued performance scaling. Through silicon via is the main structure that enables 3D integrated circuits and provides electrical connection between dies. Thermal through silicon vias are dummy vias that facilitate heat transfer across stacked dies. However, the insertion of thermal through silicon vias extends the distance between functional units and increases the signal delay. In this dissertation, we develop a hierarchical approach to optimize the floorplan of a 3D integrated circuit through simulated annealing to address the trade-off between the peak temperature, chip area, and performance. Compared to the floorplan with a fixed thermal via placement between cores, our algorithm optimally places thermal vias between functional units and offers the optimal floorplan. This dissertation presents that the use of holey silicon and through silicon vias can provide effective device-level and system-level thermal management solutions for next-generation electronic systems. Holey silicon with anisotropic thermal conductivity is ideal for lateral thermoelectric devices, which enables breakthroughs in addressing local hot spots under steady-state and transient conditions. Thermal through silicon vias reduce the peak temperature of 3D integrated circuits. The hierarchical floorplanning method that includes thermal via early in the processor design process could address the trade-off between thermal and electrical performance and provide optimal floorplans for next-generation electronic systems.

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