UC Irvine

The D-band (110–170 GHz) offers contiguous bandwidth that makes backhaul links exceeding 100 Gb/s attainable and enables sub-millimeter-resolution imaging and centimeter-resolution radar. Complementary metal-oxide-semiconductor (CMOS) technology is an attractive platform for these transmitters because it enables monolithic integration of the analog front end, digital baseband, and control circuitry on a low-cost die.The first part of this dissertation introduces the design challenges of broadband D-band transmitters. At D-band frequencies, CMOS transistors operate near half of their maximum oscillation frequency, where available gain degrades rapidly, while their low breakdown voltage limits the saturated output power of a single-stage amplifier. Meanwhile, the antenna must maintain impedance matching over a wide bandwidth. Consequently, the communication range depends on both power amplifier (PA) output power and antenna gain.The second part of this dissertation presents a three-stage broadband D-band PA fabricated in 65-nm bulk CMOS. A device-centric power model for cascode PA stages, incorporating mobility-induced transconductance compression, shows that maximum output power is achieved when the common-gate device is larger than the common-source device. Based on this observation, an enhanced power current-reuse cascode (EPCRC) stage is proposed, where a third transistor reuses the excess current from the device size mismatch while improving power gain. To overcome the bandwidth limitation of conventional combiners with large impedance transformation ratios, a four-way slotline-based dual-coupled differential power combiner (DCDPC) is proposed. The PA achieves 19-dBm peak saturated output power, 15.3-dB peak gain, 5.3% power-added efficiency (PAE), and a 32.8-GHz 3-dB bandwidth from 110–142 GHz within 0.99 × 0.48 mm2, with an error vector magnitude (EVM) of −21 dB or better up to 1024-quadrature amplitude modulation (1024-QAM).In the third part of this dissertation, two wideband antennas on a flexible printed circuit (FPC) are presented for the WR-08 band (90–140 GHz). Conventional aperture-coupled stacked-patch (ACSP) designs fail to reach a large bandwidth here, and feedline-induced surface waves reduce the radiation efficiency at several resonances. A two-section wideband distributed network (TWBDN) therefore matches the input port to the slot aperture, a TWBDN matched stacked patch (TMSP) network based on constant voltage standing wave ratio (VSWR) circles extends it to the patches. A methodology to suppress the surface waves around the feedline through via arrays is studied, and a low-loss ground-signal-ground (GSG) transition facilitates measurement. The fabricated antenna measures a 7.95-dBi peak gain and S11 at or below −10 dB from 90 to 128.5 GHz. The surface waves launched by the radiating patches themselves, however, remain and limit the gain. A cavity-backed ACSP (CB-ACSP) is therefore proposed, in which one via-wall cavity confines these waves and a second cavity intercepts the leakage admitted by the FPC minimum via spacing. The measured CB-ACSP covers 91.5–134 GHz below −10 dB, a 37.7% fractional bandwidth—the highest reported among off-chip antennas above 100 GHz—with a peak gain of 8.1 dBi.These results together establish heterogeneous integration of CMOS circuits with flexible antennas as a low-cost path to broadband high-power D-band transmitters.