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Open Access Publications from the University of California

Ab Initio Investigation of Charge Trapping Across the Crystalline-Si–Amorphous-SiO2 Interface


Accurate microscopic description of the charge-trapping process from semiconductor to defects in the dielectric-oxide layer is of paramount importance for understanding many microelectronic devices such as complementary metal-oxide-semiconductor (CMOS) transistors, as well as electrochemical reactions. Unfortunately, most current microscopic descriptions of such processes are based on empirical models with parameters fitted to experimental device performance results or simplified approximations like the Wentzel-Kramers-Brillouin (WKB) method. Some critical questions are still unanswered, including: What controls the charge-hopping rate, the coupling strength between the defect level to semiconductor level, or the energy difference? How does the hopping rate decay with defect-semiconductor distance? What is the fluctuation of the defect level, especially in amorphous dielectrics? Many of these questions can be answered by ab initio calculations. However, to date, there are few ab initio studies for this problem mainly due to technical challenges from atomic-structure construction to large-system calculations. Here, using the latest advances in calculation methods and codes, we study the carrier-trapping problem using density-functional theory (DFT) based on the Heyd-Scuseria-Ernzerhof (HSE) exchange correlation functional. The valence bond random-switching method is used to construct the crystalline-Si-amorphous-SiO2 (c-Si/a-SiO2) interfacial atomic structure, and the HSE yields a band offset that agrees well with experiments. The hopping rate is calculated with the Marcus theory, and the hopping-rate dependences on the gate potential and defect distances are revealed, as well as the range of fluctuation results from amorphous structural variation. We also analyze the result with the simple WKB model and find a major difference in the description of the coupling constant decay with the defect-semiconductor distance. Our results provide the ab initio simulation insights for this important carrier-trapping process for device operation.

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