This report describes the Chippe system, gives some background previous work and describes several sample design runs of the system. Also presented are the sources of the design tradeoffs used by Chippe, and overview of the internal design model, and experiences using the system.

This thesis presents an analytical framework and circuit solutions to a host of timing problems that are applicable to systems of varying scales. These non-standard solutions provide higher performance alternatives to the issues of multi-phase clock distribution and larger-scale on-chip or on-interposer communication and coherence. The underlying circuits for all these solutions are pulse mode asynchronous and built using a logic family of gates that encode both data and the time of arrival as atomic pulses. These gates incorporate local negative feedback loops leading to useful dynamic behavior that is exploited in the design of low-noise closed loop timing circuits.First, Collective Pulse Oscillators (or CPOs), the simplest closed loop pulse gate circuits are presented. CPOs achieve FoMs better than conventional ring oscillators, while also providing precise clock phases much finer than the delay of a typical gate in a given technology. The noise analysis of CPOs is based on a time-domain analytical model, which is expanded into a rapid behavioral simulator, and validated against measurement results for different diameter CPOs implemented in 130 nm technology. Next, complex CPO topologies that improve the high-frequency stability of loop-connected CPOs are presented and the potential of such structures in implementing timing distribution networks that utilize distributed feedback to enhance the accuracy of the timing source itself is evaluated. Architecture, design and measurement results for a 5.5 GHz low- jitter transmission-line stabilized pulsed wave oscillator implemented in 130 nm are also presented. Second, Multi-Wire Phase Encoding (MWPE), a transition signaling strategy suitable for on-chip/on-interposer links connecting globally asynchronous modules is presented. These links are aimed at reducing the energy cost of moving data across a large scale SoC or NoC, which is known to be orders of magnitude higher than the cost of computation. MWPE, by encoding data in the time correlated switching of multiple signaling wires allows very high-bandwidth data transmission on band-limited and lossy on-chip wires, with PLL/DLL free data recovery. Theoretical and practical bandwidth limits for MWPE are derived and link performance in 22 nm FDX technology is evaluated. Finally, methods of implementing low cost time-domain linear filters that utilize precise clock phases to reduce timing noise originating from systematic noise sources are presented.

This work presents a novel CMOS behavior of self stabilization of ring oscillators using collective dynamics. It shows that phase error correction can occur in ring oscillators over multiple cycles without an external reference via the collective dynamics of pulses. In time domain this shows up as timing stability improvement in oscillators. Different timing stability metrics were analyzed to determine the correct methodology to analyze this stability improvement. Behavioral models were made to capture the effects of local dynamics and its collective effects. These models were shown to have a good correlation with the HSPICE circuit simulations and measured values.

Multiple oscillator topologies and architectures were fabricated to test the model, behavior and subsequent analysis. Different pulse amplifier based ring oscillators show trends similar to that predicted by simulations and empirical relationships developed using behavioral simulations. Further transmission line stabilized traveling wave version of the pulse oscillators show a higher stability improvement.

This work opens up a new design space in the timing circuits design where all the other conventional tricks are still applicable. It also opens up an application space due to the timing stability improvement in the order of 1000 cycles where conventional ADC’s and TDC’s work. Finally this work eases up the constraints of loop filter and source phase noise when oscillators are operated in a phase locked loop.

In the search for intelligent silicon, the energy costs of traditional sensing and computation are barriers to progress and are forcing new modalities for communication, computation, and storage. Conventional signaling (discrete binary digital, analog level) suffers from non-idealities due to physical noise on large wires between miniature transistors. The errors found in the communication channels between the devices cause increased power demands because a classical computation must use enough energy to compute and transmit the answer across wires. This work combines recent advances in computation and communication, to simultaneously sense and transmit information acquired while sending the data through a spiking communication channel with additional computation capabilities.

Spiking or pulse-based asynchronous computation and communication schemes indicate additional energy bounds useful for understanding noisy answers. The use of pulse signals provide behaviorally robust and scalable system architectures for novel encoders. The encoders take advantage of hierarchical uneven fractional connectivity to transmit data during a space-time computation for the purposes of neuromorphic communication. These encoders enable semi-intelligent sensors capable of efficient data transfer from practical CMOS mixed-signal race logic integrated circuits.

Modern heterogeneous devices provide of a variety of computationally diverse components holding tremendous performance and power capability. Hardware-software cosynthesis offers system-level synthesis and optimization opportunities to realize the potential of these evolving architectures. Efficiently coordinating high-throughput data to make use of available computational resources requires a myriad of distributed local memories, caching structures, and data motion resources. In fact, storage, caching, and data transfer components comprise the majority of silicon real estate. Conventional automated approaches, unfortunately, do not effectively represent applications in a way that captures data motion and state management which dictate dominant system costs. Consequently, existing cosynthesis methods suffer from poor utility of computational resources. Automated cosynthesis tailored towards memory-centric optimizations can address the challenge, adapting partitioning, scheduling, mapping, and binding techniques to maximize overall system utility.

This research presents a novel hierarchical transaction model that formalizes state and control management through an abstract data/control encapsulation semantic. It is designed from the ground-up to enable efficient synthesis across heterogeneous system components, with an emphasis on memory capacity constraints. It intrinsically encourages a high degree of concurrency and latency tolerance, and provides verification tools to ensure correctness. A unique data/execution hierarchical encapsulation framework guarantees scalable analysis, supporting a novel concept of state and control mobility. A front-end language allows concise expression of designer intent, and is structured with synthesis in mind. Designers express families of valid executions in a minimal format through high-level dependencies, type systems, and computational relationships, allowing synthesis tools to manage lower-level details. This dissertation introduces and exercises the model, discussing language construction, demonstrating control and data-dominated applications, and presenting a synthesis path that exhibits near-linear scalability with problem size.

Abstract--- This dissertation describes a design and analysis methodology for \Sigma\Delta bitstream filters and controllers in digital hardware. These circuits emulate continuous linear time invariant (LTI) models and directly process \Sigma\Delta encoded bitstreams produced by \Sigma\Delta-based data converters. Since these converters are oversampled, there is a natural opportunity for clocking at the oversampling rate allowing for multiplierless, low latency designs. Direct processing of bitstreams also eliminates lowpass filtering and decimation necessary for conventional bit-parallel DSP. Combined, these changes reduce the hardware resources by more than an order of magnitude in FPGA implementations, with similar improvements in power overhead. MASH techniques (used extensively in data converters) are developed to allow for substantive improvement in resolution or reduction of the oversampling rate. These results have very substantive implications in the design of low-complexity, high performance controllers. In particular, these techniques can obviate conventional DSP augmented designs allowing for robust control in applications unreachable with current technology.

This thesis addresses the problem of behavioural identification and timingverification for asynchronous, pulse-gate circuits. In particular, the design of very high performance logic and control functions such as time-to-digital, data-recovery, pipeline and FIFO control logic are targeted. The objective of this work is to produce models that are sufficiently general to include these hand designed circuits, amenable to automatic timing verification and, if possible, encompass known pragmatic techniques for asynchronous closure.

To achieve this timing verification a pair of timing models are proposed. The ``unit time'' model models the local behaviour of the circuit, and a ``phrase'' model models the communication between the unit timed regions. The phrase model also leads to a model for system level behaviour.

The ``unit time'' model allows the abstract system behaviour derived from symbolic simulation of the circuit as the specification. This step uses the special behaviour of pulse gates to create the symbolic abstraction, thus identifying possible nominal `states' of model predicted behaviour and through this agreed behavioural convention the behaviour predicted by the model should agree with designer intended behaviour.

Next ``phrases'' are introduced as a model for communication between coherent unit timed regions, while the whole ensemble system need not be coherent. The whole system can be examined at a global level by modelling the set of phrases potentially currently occurring and which phrases result from these. This describes a path towards system level verification to ensure that behavioural escape does not occur due to overlaps of predicted local behaviours.

A ‘coherence depth’ property is defined to determine that gates in the local region are sufficiently connected over all logic cases for this model to be self sufficient. A formal proof that this property plus a set of critical path inequalities are sufficient to verify the timing of the system.

A computer tool is presented to derive the necessary timing constraints. Results from this tool are presented both to show the scale of problems it can handle, and that its constraints are in good agreement with SPICE for small circuits.