This report describes a new technique that combines the Hardware Scheduling and Component Selection phases for High Level Synthesis. Our technique simultaneously selects components from a given library while it schedules the operations into different control steps. The algoríthm improves previous work in scheduling because component costs and performance are considered during the scheduling process, enlarging the design search space and resulting in better optimized desígns.

The Discrete Cosine IVansform (DCT) is used in the MPEG and JPEG compression standards. Thus, the DCT component has stringent timing requirements. The high performance which is required cannot be achieved by a sequential implementation of the algorithm. In this report, we explore different optimization techniques to improve the performance of the DCT. We discuss various pipelining options to further reduce the latency. We present a transformation of the algorithm that reduces the memory requirements and hence, reduces the cost of the implementation. We also describe RT-level implementations of the sequential, pipelined and memory optimized designs.

In this report, we discuss the various issues and problems associated with ASIC reuse. We describe the different models of communication between components and the essential issues in interfacing ASICs that use different communication protocols. We come up with guidelines that help in modeling for reuse. We also propose a new HDL, SpecC, that has the desirable characteristics for co-designing systems. This language is suited for ASIC reuse and overcomes the limitations of VHDL.

In this report, we present an architectural classification based on four design features: customization, slicing direction, parallelism and pipelining. We also propose a strategy for exploring the architectural space of a design by varying these design features in a systematic way. We believe that design exploration carried out in such a manner will not only save considerable designer time and effort but also result in more cost-effective designs. In order to demonstrate the effectiveness of our exploration strategy we give the results of applying it on four examples: a timer system, an FIR filter, an FFT datapath, and a robot kinematics system.

Many high level synthesis systems produce designs without any consideration for the underlying architecture. In such systems, tradeoffs between area and delay can only be achieved by changing the synthesis constraints (e.g., number of functional units). These systems do not exploit the wider range of tradeoffs that can be achieved by modifying the underlying architecture. In this report we derive a relationship between architectural constraints and scheduling algorithms, and demonstrate how architectural styles impose certain restrictions on the scheduling process. In particular, we consider different control pipelining architectures. We also propose a versatile scheduling algorithm that is capable of synthesising designs for different control pipelining styles.

We present a specification of a general environment for behavioral synthesis centered around the user/designer as the primary motivator for decisions in design development. At each stage of the design process, the user can perform transformations on the design description through graphical user interfaces. Quality measures, physical estimates, and design hints are given to the user at each stage.

In this report we outline the main problems of communication synthesis task in the context of SpecC Environment, with focus on issues related to System-On-a-Chip design and Intellectual Property interfacing. Given an architecture model, we present the models and transformations necessary for generating the final communication model. The major refinement steps are also discussed in various abstraction levels and for various types of communicating parties (hardware, software).

Embedded system designers continuously face a twofold challenge handling the ever-

increasing complexity of design and meeting the ever-shrinking time-to-market timeline. To meet such a challenge, the system design paradigm has shifted to platform-based design characterized by intensive use of software and aggressive reuse of verified components. More and more designs are turning to heterogeneous platforms to meet design constraints in multiple criteria. However, the use of such and heterogeneity generates more challenges for platform-based design. To address the challenges, system designers must utilize system-level methodologies for specification and design. Here the designers begin the design process by coming up with a computation model

that captures the behavior of the system. The computation model is successively refined down to the structural model in the system level. In each refinement, the designers explore the design space. The design space comprises a set of alternatives concerning hardware/software partitioning, platform selection, and mapping. The design space is huge, however, necessitating the automation of its exploration. The platform is very often fixed regarding either availability or legacy reasons, making mapping crucial. This dissertation focuses on the automatic mapping of the computation model for the given heterogeneous platform.

This dissertation presents a new automatic mapping technique. The proposed technique consists of two separate phases: initial mapping and improvement driven by cycle-approximate estimation. Existing mapping techniques depend on early estimation so a dilemma arises from the fact that cycle-approximate estimation cannot precede mapping. The dilemma can be gotten around by our performing initial mapping based on rough estimation and then making iterative improvements based on cycle-approximate estimation. While earlier work has been domain specific, the mapping techniques in the proposed work are driven by a general computation model that includes hierarchy, state transitions, dynamic data-oriented behavior, and imperative languages. The proposed work also addresses mapping with an awareness of general hierarchy in pipelined applications. In such a mapping technique, the size of the design space explored is limited by

the speed of cycle-approximate estimation. Earlier work has realized such a fast cycle-approximate estimation by generating and simulating Transaction Level Models. However, simulation has to be performed whenever there is any change in the platform or mapping. That is not necessary and therefore there is still room for improvement regarding speed. This dissertation presents a new trace-driven estimation that is orders of magnitude faster than simulation-based cycle-approximate estimation while losing neither accuracy nor generality.

We have applied the proposed mapping techniques to multiple multimedia applications and the techniques outperformed in terms of execution time the competitors by proportions ranging from 23.3% through 36.3%.

This work describes an integrated design methodology focusing on power exploration at behavioral level. We present a behavioral-level tool for architecture selection and power estimation within the SpecSyn [GVNG94] environment. The implementation has two major steps of scheduling and power estimation. Power analysis is done in both steps; it is approximate in the former and detailed in the latter. A combination of empirical and analytical approaches is used for power estimation. We provide several case studies of common benchmarks to illustrate the design methodology as also its interactive and efficient nature that enables fuller design space exploration. We evaluate power versus performance trade-offs for different implementations of each example, using our tool. An important premise for this work is accurate characterisation of resource library for power.