Functional verification of RTL is one of the primary and most time consuming tasks of microprocessor design. However, designs cannot be completely verified due to their large size and strict time-to-market restrictions. Formal verification and simulation-based verification both sacrifice completeness for utility. While formal verification is relegated to the verification of a part or an abstraction of the design, dynamic verification reduces complexity by restricting possible input sequences. Being more scalable, simulation-based verification has been the mainstay of functional verification.
A majority of simulated tests are created from separate, automatic, random stimuli generators based on user templates. The generated stimuli, usually in the form of assembly programs, trigger architectural and microarchitectural events. The quality of applied tests is periodically evaluated based on coverage points defined in a verification plan.
On one hand, the use of randomization inevitably leaves some redundancy in the generated tests. On the other hand, the effectiveness of a generator depends on the fact that test templates are user defined. Because of these limitations, it is challenging to develop a new generator that out-performs an existing generator in every aspect. As a result, over the years multiple test generators are developed and retained, incurring tremendous overhead in maintaining the software infrastructure.
In this thesis we propose a novel methodology to improve the effectiveness of one test generator with respect to another. First, we evaluate the effectiveness of using a legacy test generator used at AMD and quantify its verification performance. We explore the differences in the design and capabilities between the legacy test generator and AMD's latest in-house x86 ISA-based test generator. We then proceed to gather experimental evidence to support our understanding. Functional coverage measurements based on an existing verification plan confirm our findings. With the exception of two cases, we find the latest test generator to have a far superior capability for verifying the features tested. The two exceptions are due to its design limitations. We propose to utilize external test filters to overcome these limitations.
We develop a test filtration approach that is independent of the test generator, to filter out ineffective tests prior to RTL simulation. We achieve this by using ISA simulation traces. We find that using a combination of ISA simulation traces and microarchitectural models is necessary to cover a wider range of coverpoints. Our work shows that by using implementation specific details for extrapolating test behavior information present in simulation traces, we can compensate for microarchitecture agnostic test generation and consequently improve the effectiveness of a test generator without modifying its design. The proposed approach expedites coverage closure by providing precise control over random test behavior. Experimental results based on the latest AMD multi-core processor design are presented to demonstrate the feasibility of our proposed approach.